1. Field of the Invention
The present invention relates to a nonvolatile memory cell string and a NAND flash memory array using the same. Additionally, the present invention also relates to neuromorphic technologies mimicking a synapse, a synapse array and functions of neurons and synapses.
2. Description of the Related Art
To increase the degree of integration in a NAND flash memory etc., memory cell devices and structures of memory cell strings thereof connected in series have been continuously studied.
In the recently spotlighted technologies mimicking the functions of neurons and synapses, high integrated memories and strings and arrays connected with the memories are increasingly needed. The functions of synapses can be mimicked by the memory devices, but it is needed to have some excellent characteristics such as reliability, low power, low noise and reproducibility etc. Especially, when human brain is mimicked, it is needed to highly increase the degree of integration because about 1014 synapses have to be embodied by the memory cells.
FinFET has been developed to overcome the problems of conventional plane-type devices such as a short channel effect (SCE), a low read current due to the leakage currents and a drain induced barrier lowering (DIBL) etc.
Though the FinFET structure can solve the problems of the above mentioned plane structure, it is always have another problem associated with a high integration because of a limitation in reducing width of a fin needed in one cell and that of oxide/nitride/oxide (ONO) layers formed on the both sides of the fin.
To solve the problem of the conventional FinFET structure, Korean Patent No. 10-0745766 (refer to patent reference 1) provides techniques for increasing the degree of integration by reducing the fin separation distance between adjacent cells through isolating two fin structures with a buried insulating layer and simply wrapping the two fins with a gate electrode interlaying a gate insulating layer.
By the way, the patent reference 1 shows that the isolated two fin structures interlaying a buried insulating layer forms adjacent cell strings and each cell string contains a plurality of cell devices and at least two switch devices. The FET based cell devices oppositely formed to each other interlaying the buried insulating layer have a problem changing threshold voltage of devices due to the interference to each other. Two adjacent cell strings isolated by the buried insulting layer need a cell string contact pad having 3 times wider width than that of the conventional cell string and a common source line (CSL) contact pad on both end sides, respectively and it causes an loss of area. Especially, formation of the pads for contacting to metal interlaying the buried insulating layer with a narrow width causes a design rule matter and so it needs to consume more area.
And the conventional NAND flash memory array, as shown in FIG. 10, necessarily has a string selection line (SSL) for selecting cell string and a common source line (CSL) and a ground selection line (GSL) for selecting CSL on both sides of each memory string.
By the way, because SSL and GSL are conventionally formed to have a line width 4˜5 times more than that of each word line (it means that selection transistors selected by SSL and GSL are formed with an area 4˜5 times more than that of memory device formed by each word line), the area loss is one of reasons preventing a high integration.
The above mentioned problem takes place by reading a current flowing between a bit line connected to a specific cell string and CSL after being always turned on the selection transistors by SSL and GSL on reading any cell in the specific cell string of the conventional NAND flash memory.